A Configurable ULP Instrumentation Amplifier with Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS

Dekimpe, Rémi;Bol, David
(2021) IEEE Transactions on Circuits and Systems. Part 2: Express Briefs — Vol. 68, n° 7, p. 2272-2276 (2021)

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Performance trade-offs are central to analog/mixed-signal circuit design as they define the boundaries of the achievable design space. Circuit configurability allows run-time dynamic adaptation of these performance trade-offs to variable operating conditions. In this work, a new design methodology is used to implement an ultra-low-power (ULP) Pareto-optimal biomedical instrumentation amplifier (IA) with configurable power-noise trade-off. A multi-objective genetic algorithm performs the numerical optimization of the parameters at design time. The non-dominated sorting genetic algorithm (NSGA-II) is used along with an efficient simulation framework to limit the computation time. The optimal sizing is then applied to selected devices with digitally-controlled parameters in the amplifier. The configurable IA for biomedical applications has been prototyped in 65nm LP CMOS. It can be digitally set to 4 operating modes with power consumption ranging from 0.56 to 23.8µW and input-referred noise from 1µV to 0.17µV. The minimum noise efficiency factor (NEF) achieved by the amplifier is 1.93. The silicon area is 0.055mm² excluding the off-chip high-pass filter.
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Dekimpe, R., & Bol, D. (2021). A Configurable ULP Instrumentation Amplifier with Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS. IEEE Transactions on Circuits and Systems. Part 2: Express Briefs, 68(7), 2272-2276. https://doi.org/10.1109/TCSII.2021.3059311 (Original work published 2021)