Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications
(2004) Proceedings of ITCC 2004 — Location: Las Vegas, USA (April.2004)
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- Authors
Legat, Jean-Didier 
- Abstract
- Hardware implementations of the Advanced Encryption Standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe efficient architectures for ASICs (ASIC: Application Specific Integrated Circuit) and FPGAs (FPGA: Field Programmable Gate Array). In this context, the highest effort was devoted to high throughput (up to 20 Gbps) encryptiononly designs, fewer works studied low area encryptiononly architectures and only a few papers have investigated low area encryption/decryption structures. However, in practice, only a few applications need throughput up to 20 Gbps while flexible and low cost encryption/decryption solutions are needed to protect sensible data, especially for embedded hardware applications. This paper proposes an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints. The proposed design fits into the smallest Xilinx FPGAs (Xilinx Spartan-3 XC3S50), deals with data streams of 208 Mbps, uses 163 slices and 3 RAM blocks and improves by 68% the best-known similar designs in terms of ratio Throughput=Area. We also propose implementations in other FPGA Families (Xilinx Virtex-II) and comparisons with similar DES, triple-DES and AES implementations.
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Citations
Rouvroy, G., Standaert, F.-X., Quisquater, J.-J., & Legat, J.-D. (2004). Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications. Proceedings of ITCC 2004, Las Vegas, USA. https://hdl.handle.net/2078.5/252927