Very low Schottky barrier to n-type silicon with PtEr-stack silicide

Tang, Xiaohui;Katcki, J.;Dubois, Emmanuel;Ratajczak, J.;Bayot, Vincent;et.al.
(2003) 203th Meeting of the Electrochemical Society 2003 — Location: Paris (France) (28.April.2003)

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Authors
  • Tang, XiaohuiUCLouvain
    Author
  • Katcki, J.Institute of Electron Technology, Warsaw
    Author
  • Dubois, EmmanuelIEMN/ISEN, Villeneuve d'Ascq
    Author
  • Ratajczak, J.Institute Of Electron Technology, Warsaw
    Author
  • Loumaye, PierreUCLouvain
    Author
  • Nisole, OlivierUCLouvain
    Author
  • Bayot, VincentUCLouvain
    Author
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Abstract
We investigate Er silicide formed on n-type silicon. In order to protect Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprinsingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at 600°C. A simplified method of analysis considering the final Schottky-barrier SOI-MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low Schottky barrier (smaller than 0.1eV) on a n-type substrate with a concentration of 1.4x10exp.16 cm³ in the active region has been obtained.
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Tang, X., Katcki, J., Dubois, E., Ratajczak, J., Larrieu, G., Loumaye, P., Nisole, O., & Bayot, V. (2003). Very low Schottky barrier to n-type silicon with PtEr-stack silicide. 203th Meeting of the Electrochemical Society 2003, Paris (France). https://hdl.handle.net/2078.5/201133