Improved LOCOS isolation for thin-film SOI MOSFETs

Colinge, JP.;Crahay, André;Deceuster, D.;Dessard, V.;Gentinne, B.
(1996) Electronics Letters — Vol. 32, n° 19, p. 1834-1835 (1996)

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Authors
  • Colinge, JP.
    Author
  • Crahay, AndréUCLouvain
    Author
  • Deceuster, D.
    Author
  • Dessard, V.
    Author
  • Gentinne, B.
    Author
Abstract
The authors propose the use of a recessed LOCOS technique instead of a standard LOCOS process to eliminate parasitic edge transistor leakage in thin-film SOI MOSFETs. This technique helps to increase the sidewall threshold voltage by both avoiding excess boron segregation into the field oxide, and providing a smoother edge rounding than that obtained by a classical LOCOS process.
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Colinge, JP., Crahay, A., Deceuster, D., Dessard, V., & Gentinne, B. (1996). Improved LOCOS isolation for thin-film SOI MOSFETs. Electronics Letters, 32(19), 1834-1835. https://doi.org/10.1049/el:19961210 (Original work published 1996)