On-chip tensile testing of nanoscale silicon free-standing beams
(2012) Journal of Materials Research — Vol. 27, n° 3, p. 571-579 (2012)
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- Authors
- Abstract
- Nanomechanical testing of silicon is primarily motivated toward characterizing scale effects on the mechanical behavior. “Defect-free” nanoscale silicon additionally offers a road to large deformation permitting the investigation of transport characteristics and surface instabilities of a significantly perturbed atomic arrangement. The need for developing simple and generic characterization tools to deform free-standing silicon beams down to the nanometer scale, sufficiently equipped to investigate both the mechanical properties and the carrier transport under large strains, has been met in this research through the design of a versatile lab-on-chip. The original on-chip characterization technique has been applied to monocrystalline Si beams produced from Silicon-on-Insulator wafers. The Young’s modulus was observed to decrease from 160 GPa down to 108 GPa when varying the thickness from 200 down to 50 nm. The fracture strain increases when decreasing the volume of the test specimen to reach 5% in the smallest samples. Additionally, atomic force microscope-based characterizations reveal that the surface roughness decreases by a factor of 5 when deforming by 2% the Si specimen. Proof of concept transport measurements were also performed under deformation up till 3.5% on 40-nm-thick lightly p-doped silicon beams.
- Affiliations
Newcastle University School of Electrical, Electronic & Computer Engineering
Citations
Bhaskar, U. K., Passi, V., Houri, S., Escobedo-Cousin, E., Olsen, S. H., Pardoen, T., & Raskin, J.-P. (2012). On-chip tensile testing of nanoscale silicon free-standing beams. Journal of Materials Research, 27(3), 571-579. https://doi.org/10.1557/jmr.2011.340 (Original work published 2012)