An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

Haine, Thomas;Nguyen, Quoc-Khoi;Stas, François;Moreau, Ludovic;Bol, David;et.al.
(2017) 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017) — Location: Leuven (Belgium) (11.September.2017)

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An80-MHz04VULVSRAMmacroin28nmFDSOIachieving28-fJ-bitaccessenergywithaULPbitcellandon-chipadaptivebackbiasgeneration.pdf
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Authors
  • Haine, ThomasUCLouvain
    Author
  • Nguyen, Quoc-KhoiUCLouvain
    Author
  • Stas, FrançoisUCLouvain
    Author
  • Moreau, LudovicUCLouvain
    Author
  • Flandre, DenisUCLouvain
    Author
  • Bol, Davidorcid-logoUCLouvain
    Author
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Abstract
In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low Vt (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB macro. Process voltage temperature (PVT) compensation is performed on-chip by an adaptive back biasing (ABB) generator. At 0.4V, the proposed SRAM can operate at 80 MHz and reaches access energy of 28 fJ/bit including the ABB generator in closed-loop operation.
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Haine, T., Nguyen, Q.-K., Stas, F., Moreau, L., Flandre, D., & Bol, D. (2017). An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017), Leuven (Belgium). https://hdl.handle.net/2078.5/252631