Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate

Lederer, D.;Aspar, B.;Laghaé, C.;Raskin, Jean-Pierre
(2006) IEEE International SOI Conference, SOI’06 — Location: Niagara Falls, New York (USA) (2.October.2006)

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High Resistivity (HR) silicon wafers are promising candidates for RF applications due, mainly, to their low cost, CMOS compatibility and substantial substrate loss reduction [1]. However, oxidized HR silicon (such as HR SOI material) is known to suffer from parasitic surface conduction (PSC) below the oxide [2], which can reduce the effective resistivity ( ρ eff) of the wafers by more than one order of magnitude [3]. This issue can be overcome by introducing a trap-rich passivation layer between the oxide and the Si substrate, such as polysilicon [2]. In this paper we demonstrate for the first time that: (1) polySi substrate passivation can be efficiently realized on an industrial SOI technology using a post-process circuit transfer technique and that: (2) this technique preserves the performance of active devices.
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Lederer, D., Aspar, B., Laghaé, C., & Raskin, J.-P. (2006). Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate. IEEE International SOI Conference, SOI’06, Niagara Falls, New York (USA). https://hdl.handle.net/2078.5/228599