A survey of multistep A to D converters and error correction mechanisms
(2005) SBCCI 2005. 18th Symposium on Integrated Circuits and Systems Design — Location: Florianopolis, Brazil (4.September.2005)
Files
No attached file found for this publication.
Details
- Authors
- Abstract
- Summary form only given. Multistep converters do better than delta sigma converters in terms of speed but they are less accurate. Breaking the conversion process in two or three steps eases naturally the design of the internal flash and parallel sub-converters but imposes stringent requirements as far as tolerances. The number of bits resolved per cycle has a distinct impact on the overall performances. Errors caused by the A to D sub-converter may be compensated numerically by means of redundant representations such as the R.S.D. algorithm. Errors caused in the subsequent D to A converter are taken care of by more elaborated correction algorithms. Interstage gain and bandwidth set the ultimate performances. On the whole the relative importance of these impairments depends strongly on the type of application.
- Affiliations
Citations
Jespers, P. (2005). A survey of multistep A to D converters and error correction mechanisms. SBCCI 2005. 18th Symposium on Integrated Circuits and Systems Design(IEEE Cat. No. 05EX1196), p. 7. https://hdl.handle.net/2078.5/222321