Design strategies and modified descriptions to optimize cipher FPGA implementations: Fast and compact results for DES and triple-DES

Rouvroy, G.;Quisquater, Jean-Jacques;Legat, Jean-Didier;Standaert, François-Xavier
(2003) 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) — Location: LISBON(Portugal) (1.September.2003)

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In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with 116 dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.
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Rouvroy, G., Quisquater, J.-J., Legat, J.-D., & Standaert, F.-X. (2003). Design strategies and modified descriptions to optimize cipher FPGA implementations: Fast and compact results for DES and triple-DES. Lecture Notes in Computer Science, 2778, 181-193. https://hdl.handle.net/2078.5/252481 (Original work published 2003)