Word-parallel CRC computation on VLIW DSP

Hubaux, D;Legat, Jean-Didier
(2002) Electronics Letters — Vol. 38, n° 2, p. 64-65 (2002)

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  • Hubaux, D
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  • Legat, Jean-Didierorcid-logoUCLouvain
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Abstract
Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using. the toll power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method to at least four times faster for 8, 16 and 32 bits CRC.
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Hubaux, D., & Legat, J.-D. (2002). Word-parallel CRC computation on VLIW DSP. Electronics Letters, 38(2), 64-65. https://doi.org/10.1049/el:20020047 (Original work published 2002)