A systolic array for SVD updating

Moonen, M.;Van Dooren, Paul;Vandewalle, J.
(1998) High performance VLSI signal processing, innovative architectures and algorithms-II — ISBN: [0-7803-3469-8], p. 29-47, published

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  • Moonen, M.KULeuven
    Author
  • Van Dooren, PaulUCLouvain
    Author
  • Vandewalle, J.KULeuven
    Author
Abstract
In an earlier paper, an approximate SVD updating scheme has been derived as an interlacing of a QR updating on the one hand and a Jacobi-type SVD procedure on the other hand, possibly supplemented with a certain re-orthogonalization scheme. This paper maps this updating algorithm onto a systolic array with O(n2) parallelism for O(n2) complexity, resulting in an O(n0) throughput. Furthermore, it is shown how a square root-free implementation is obtained by combining modified Givens rotations with approximate SVD schemes.
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Moonen, M., Van Dooren, P., & Vandewalle, J. (1998). A systolic array for SVD updating. In K.J.R. Liu, Yao K. (ed.), High performance VLSI signal processing, innovative architectures and algorithms-II (p. p. 29-47). IEEE Press. https://hdl.handle.net/2078.5/82297