Logic verification of incomplete functions and design error location
(1993) Correct Hardware Design and Verification Methods. IFIP WG10.2 Advanced Research Working Conference CHARME ’93 Proceedings — Location: Arles, France (24.May.1993)
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- Abstract
- At the stage of logic verification, it is necessary not only to detect but also to locate the sources of design errors that may exist in the gate-level circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified to be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation is described.
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Citations
Zhang, Q., & Trullemans, C. (1993). Logic verification of incomplete functions and design error location. In Milne, G.J.; Pierre, L.; (ed.), Correct Hardware Design and Verification Methods. IFIP WG10.2 AdvancedResearch Working Conference CHARME ’93 Proceedings (p. p. 68-79). Springer-verlag. https://hdl.handle.net/2078.5/220442