DTMOS low noise amplifier design in partially depleted SOI CMOS technology
(2006) 2006 IEEE International SOI Conference — Location: Niagara Falls, NY, USA (2.October.2006)
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- Abstract
- This paper reviews and analyzes a low-noise amplifier (LNA) for low-power applications using a cascode inductive source degeneration topology, with a dynamic threshold MOSFET (DTMOS) transistor in 130 nm CMOS SOI technology. Thanks to the introduction of dynamic threshold-voltage MOSFET (DTMOS), the measurement of the LNA shows 13 dB gain and -30 dB reflection input, while dissipating 6 mW under 1.2 V supply.
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Citations
El Kaamouchi, M., Si Moussa, M., Raskin, J.-P., & Vanhoenacker-Janvier, D. (2006). DTMOS low noise amplifier design in partially depleted SOI CMOS technology. 2006 IEEE International SOI Conference (IEEE Cat. No. 06CH37786), p. 127-128. https://doi.org/10.1109/SOI.2006.284468