Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications
(2014)
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- Abstract
- The Internet-of-Things (IoT) is an emerging paradigm that aims to integrate technology into the human environment, rather than the reverse. By connecting together a multitude of sensors and devices, through cross-correlation and increased contextual awareness, interactions with such connected devices is set to become more relevant and less intrusive. At the heart of this IoT are the individual Wireless Sensor Nodes (WSNs), which are limited in their autonomy by the energy they can store or harvest. This thesis therefore aims to decrease the energy consumption of these nodes in an effort to increase their lifespans. Three main techniques were developed in this thesis to achieve that goal. Firstly, a processor was developed to provide high performance for a low average energy consumption (7.7µW/MHz at 50MHz). This enables on-node processing, thereby reducing the usage of the power-hungry wireless link. Secondly, a circuit design technique was developed to increase the average speed of combinatorial circuit blocks beyond that traditionally achievable, by adjusting the processing time to the data actually encountered, rather than the theoretical worst-case. By increasing the processing speed, the node can complete operations faster, thus allowing longer sleep times and lower overall energy consumption. Lastly, in view of the wide range of potential processing requirements inherent in WSN applications, a dual-processor technique was developed to better match each situation. Transparent from a user’s perspective, the resulting system can meet high-performance targets while at the same time process low-priority tasks during 'idle' periods. Together, the techniques proposed in this thesis can enable lower-power systems, and is a step towards a new generation of exciting applications.
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Citations
Botman, F. (2014). Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications. https://hdl.handle.net/2078.5/55360