Study of parallelism between memory accesses for multi-banked cache architectures
(2006) ACES′06, Architecture & Compilers for Embedded Systems — Location: Ter Elst, Edegem (Belgium) (3.October.2006)
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Legat, Jean-Didier 
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Loiselle, I., Delavallée, T., Manet, P., Vandierendonck, H., & Legat, J.-D. (2006). Study of parallelism between memory accesses for multi-banked cache architectures. ACES′06, Architecture & Compilers for Embedded Systems, Ter Elst, Edegem (Belgium). https://hdl.handle.net/2078.5/252783