FPGA Implementations of eSTREAM Phase-2 Focus Candidates with Hardware Profile
(2007) Proceedings of SASC 2007 — Location: Bochum/Germany
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- Efficient cryptographic implementations are a fundamental factor in the achievement and dissemination of new computerized applications. In some recent environments with (very) limited resources such as smart cards, sensor networks or RFID tags, standard algorithms may not be completely adapted.Consequently, the design of new solutions for low-cost cryptography is sometimes necessary and is at least an interesting research direction. In this context, stream ciphers are usually believed to be an efficient alternative to block ciphers, because of a lower hardware (or even software) implementation cost. The eSTREAM research initiative was consequently established in order to investigate the possibility of building secure and efficient stream ciphers. Among a large number of submitted candidates, the project recently (September 2006) narrowed the “hardware profiled” stream ciphers to four focused candidates, namely Trivium, Grain-128, MICKEY-128 2.0 and Phelix. In this paper, we evaluate the hardware performance of these algorithms in the reconfigurable hardware Xilinx Virtex-II devices. Based on our implementations (that mainly confirm previous results), we discuss the respective interest of the focused candidates and suggest certain guidelines for their comparison.
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Bulens, P., Kalach, K., Standaert, F.-X., & Quisquater, J.-J. (2007). FPGA Implementations of eSTREAM Phase-2 Focus Candidates with Hardware Profile. Proceedings of SASC 2007, Bochum/Germany. https://hdl.handle.net/2078.5/228130