Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design

Kranti, A.;Rashmi;Burignat, S.;Raskin, Jean-Pierre;Armstrong, G.A.
(2010) 2010 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2010) — Location: New Orleans, LA, USA (11.January.2010)

Files

No attached file found for this publication.

Details

Authors
  • Kranti, A.
    Author
  • Rashmi
    Author
  • Burignat, S.
    Author
  • Raskin, Jean-PierreUCLouvain
    Author
  • Armstrong, G.A.
    Author
Abstract
In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (A/sub VO/) and cut-off frequency (f/sub T/) along with a broader analog `sweet spot' in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (~10 mu A/ mu m) but extend up to 100 mu A/ mu m which corresponds to optimum A/sub VO/ and f/sub T/ performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in f/sub T/ along with a 2 fold enhancement in A/sub VO/. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.
Affiliations

Citations

  • APA
  • Chicago
  • FWB

Kranti, A., Rashmi, Burignat, S., Raskin, J.-P., & Armstrong, G. A. (2010). Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design. 2010 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2010), p. 45-48. https://doi.org/10.1109/SMIC.2010.5422943