Multi-VT ultra-low-power FPGA implementation in 65nm CMOS technology
(2012) Faible Tension Faible Consommation (FTFC), 2012 IEEE — Location: Paris (France) (6.June.2012)
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- Abstract
- The development of sustainable and durable ultra- low-power SoC calls for flexibility integration in the design flow. Reconfigurable logic circumvents the intrinsic low speed performances of software processing in microcontrollers but FPGA fabrics to be embedded suffer from a high power overhead compared to dedicated ASICs. We show that, by combining a power-oriented implementation using multi-VT , a careful repar- tition of different MOS flavors, and an aggressive scaling of core voltage, the dynamic power consumption can be reduced below 6μW/tile at 50MHz switching target and the leakage power consumption can be brought down below 0.5μW/tile. Simulation results show that a 16-bits multiplier, mapped onto the fabric developed with these techniques, is characterized by an energy per cycle as low as 2.5pJ.
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Citations
de Streel, G., Bol, D., & Legat, J.-D. (2012). Multi-VT ultra-low-power FPGA implementation in 65nm CMOS technology. Faible Tension Faible Consommation (FTFC), 2012 IEEE, p. 4 pages. https://doi.org/10.1109/FTFC.2012.6231745