Improvement of sub 0.25 µm fully-depleted SOI CMOS analog performance by thinning the Si film
(2001) Tenth International Symposium on Silicon-on-Insulator Technology and Devices — Location: Washington, DC (USA) (25.March.2001)
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Nève de Mévergnies, A., Dessard, V., Delatte, P., Brodeoux, V., Iniguez, B., Rauly, E., & Flandre, D. (2001). Improvement of sub 0.25 µm fully-depleted SOI CMOS analog performance by thinning the Si film. Electrochemical Society. Proceedings, 2001(3), 271-276. https://hdl.handle.net/2078.5/252443 (Original work published 2001)