Design of a Robust and Ultra-Low-Voltage Pulse-Triggered Flip-Flop in 28nm UTBB-FDSOI Technology
(2013) 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2013) — Location: Monterey, CA (USA) (7.October.2013)
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DeisgnofaRobustandUltra-Low-VoltagePulse-TriggeredFlip-Flopin28nmUTBB-FDSOITechnology.pdf
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- Authors
Legat, Jean-Didier 
- Abstract
- So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.
- Affiliations
Citations
Bernard, S., Valentian, A., Belleville, M., Bol, D., & Legat, J.-D. (2013). Design of a Robust and Ultra-Low-Voltage Pulse-Triggered Flip-Flop in 28nm UTBB-FDSOI Technology. 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2013), Monterey, CA (USA). https://doi.org/10.1109/S3S.2013.6716555