Backgate bias and stress level impact on giant piezoresistance effect in thin silicon films and nanowires

Passi, Vikram;Ravaux, F.;Dubois, Emmanuel;Raskin, Jean-Pierre
(2010) 23rd IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2010) — Location: Wanchai, Hong Kong, China (24.January.2010)

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  • Passi, VikramUCLouvain
    Author
  • Ravaux, F.
    Author
  • Dubois, EmmanuelUCLouvain
    Author
  • Raskin, Jean-PierreUCLouvain
    Author
Abstract
Top-down fabrication and electrical characterization of undoped p-type silicon nanowires with and without stress using a 4-point bending fixture are shown. Uniaxial tensile stress values of around 200 MPa are possible with the bending fixture. Giant piezoresistance is measured for wires of 50 nm-thick and widths from 25 nm to 1 mu m. Nonlinear characteristics at high stress level and impact of backgate bias on piezoresistance coefficient are presented for the first time.
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Passi, V., Ravaux, F., Dubois, E., & Raskin, J.-P. (2010). Backgate bias and stress level impact on giant piezoresistance effect in thin silicon films and nanowires. 23rd IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2010), p. 464-467. https://doi.org/10.1109/MEMSYS.2010.5442464