Wideband characterization of advanced SOI material and MOS devices for high frequency applications

(2006)

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Authors
Supervisors
Raskin, Jean-Pierre
Abstract
This work contributes to the assessment of the performance of the SOI technology for current and future analogue/RF applications. The investigation was performed in the context of both passive and active device integration. In Chapters 2 and 3, the investigation performed on passive devices mainly focused on the evaluation of the substrate performance, which largely determines that of passive devices such as transmission lines and inductors. This investigation confirmed that a substantial enhancement of the device electrical characteristics can be obtained by using high resistivity (HR) substrates instead of standard resistivity substrates. However, the major part of the work showed that the effective resistivity (ρ-eff) of HR SOI wafers can be strongly affected by parasitic conduction at the substrate surface, and that, in general, the value of ρ-eff is at least one order of magnitude lower than the nominal wafer resistivity (≅ 10 kΩ.cm). This generates additional losses in the substrate and, strictly speaking, the wafers can no longer be considered as lossless despite what could have been hoped by using such a type of substrate. In particular noticeable increases in CPW line losses and crosstalk level were observed on the non-passivated HR SOI wafers. Line losses can be reduced by stacking higher numbers of metal levels, but crosstalk issues are expected to even worsen in future generations of SOI wafers for which a reduction of the BOX thickness is envisaged in order to reduce self heating and short channel effects. BOX thickness reduction in combination with parasitic substrate conduction (PSC) in HR SOI wafers might also lead to an increase of undesired S/D coupling in short length devices. Such coupling is known to increase the device output conductance, thereby altering their performance for analogue/RF applications.
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Citations

Raskin, J.-P. (2006). Wideband characterization of advanced SOI material and MOS devices for high frequency applications. https://hdl.handle.net/2078.5/236060