Very low Schottky barrier to n-type silicon with PtEr-stack silicide
(2003) Solid-State Electronics — Vol. 47, n° 11, p. 2105-2111 (2003)
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- Abstract
- We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 degreesC. We find that silicidation process is fully completed by rapid thermal annealing at 500 degreesC. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4 x 10(16) cm(-3) in the active region has been obtained. (C) 2003 Elsevier Ltd. All rights reserved.
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Tang, X., Katcki, J., Dubois, E., Reckinger, N., Ratajczak, J., Larrieu, G., Loumaye, P., Nisole, O., & Bayot, V. (2003). Very low Schottky barrier to n-type silicon with PtEr-stack silicide. Solid-State Electronics, 47(11), 2105-2111. https://doi.org/10.1016/S0038-1101(03)00256-9 (Original work published 2003)