FPGA implementations of the ICEBERG block cipher
(2007) Integration : the V L S I journal — Vol. 40, n° 1, p. 20-27 (2007)
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- Abstract
- This paper presents field programmable gate array (FPGA) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt (E/D) mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and E/D agility allow considering new encryption modes to counteract certain side-channel attacks. (C) 2006 Elsevier B.V. All rights reserved.
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Standaert, F.-X., Quisquater, J.-J., Piret, G., & Rouvroy, G. (2007). FPGA implementations of the ICEBERG block cipher. Integration : the V L S I journal, 40(1), 20-27. https://doi.org/10.1016/j.vlsi.2005.12.008 (Original work published 2007)