Noise modeling and performance of SOI MOSFETs

Danneville, F.;Pailloncy, G.;Iniguez, B.;Raskin, Jean-Pierre;Dambrine, G.
(2004) IEEE MTT-S International Microwave Symposium – Workshop on high frequency noise in advanced Silicon-based devices: from basics to state-of-the-art device and circuit performances — Location: Fort Worth, Texas, USA (6.June.2004)

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  • Danneville, F.IEMN, Villeneuve d'Ascq, France
    Author
  • Pailloncy, G.IEMN, Villeneuve d'Ascq, France
    Author
  • Iniguez, B.Univ. Rovira i Virgili, Tarragona, Spain
    Author
  • Raskin, Jean-PierreUCLouvain
    Author
  • Dambrine, G.IEMN, Villeneuve d'Ascq, France
    Author
Abstract
In this paper, we are presenting a noise modeling technique in fully depleted (FD) SOI MOSFET. Starting from a physical compact model which allows us to capture the physics in such devices, an original microscopic noise model, suitable to calculate the noise performance of any field effect transistor, is developed. The method is applied to study the noise properties of FD SOI MOSFETs (0.25 μm physical gate length, 0.16 μm effective gate length); this includes a discussion at a microscopic level, the calculation of the usual P, R, C parameters (close to the device physics) and of the noise performances, taking into account extrinsic elements. To conclude, a discussion related to the noise performances as a function of the down-scaling is proposed.
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Danneville, F., Pailloncy, G., Iniguez, B., Raskin, J.-P., & Dambrine, G. (2004). Noise modeling and performance of SOI MOSFETs. Proceedings of the IEEE MTT-S International Microwave Symposium – Workshop on high frequency noise in advanced Silicon-based devices: from basics to state-of-the-art device and circuit performances, p. Paper WSN2. https://hdl.handle.net/2078.5/229263