A Cmos 13-b Cyclic Rsd A/d Converter
(1992) IEEE Journal of Solid State Circuits — Vol. 27, n° 7, p. 957-965 (1992)
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- Abstract
- A 13-b CMOS cyclic A/D converter that does not need trimming nor digital calibration is presented. The effects associated with the error on the gain factor 2 as well as the offset errors are corrected by taking full advantage of the redundant signed digit (RSD) principle. The gain error resulting from mismatches among switched capacitors is corrected by a novel strategy that implements an exact multiplication by four after two cycles. As a result, offset errors do not affect the integral or the differential linearities from the RSD algorithm. The remaining overall shift caused by offsets is reduced under the LSB level by a proper choice of capacitor switching sequence. The converter achieves 1/2 LSB integral and differential linearity at 25 kS/s; harmonic distortion is less than -83 dB. Chip area is 2.9 mm2 in a standard CMOS 3-mu-m technology, including control logic and the serial-to-parallel output shift register. Power consumption is 45 mW under +/-5-V supplies.
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Citations
Ginetti, B., Jespers, PGA., & Vandemeulebroecke, A. (1992). A Cmos 13-b Cyclic Rsd A/d Converter. IEEE Journal of Solid State Circuits, 27(7), 957-965. https://doi.org/10.1109/JSSC.1992.854935 (Original work published 1992)