A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells
(2019) 2019 IEEE International Symposium on Circuits and Systems (ISCAS 2019) — Location: Sapporo (Japan) (26.May.2019)
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A04V05fJpercycleTSPCFlip-Flopin65nmLPCMOSwithRetentionModeControlledbyClock-GatingCells.pdf
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- Abstract
- In this paper, we propose a low-overhead solution to ensure contention-free data retention in clock-gated true single-phase-clock (TSPC) flip-flops (FF) at ultra-low voltage (ULV). It relies on a retention feedback loop added to the TSPC FF and controlled by the clock-gating module. When the clock is gated, the retention is enabled, which drives the FF in retention mode. This limits the energy overhead induced by the added feedback loop and makes the FF contention-free. Moreover, as several FFs typically share the same clock-gating module, the control signal generation overhead is also kept low. The proposed 19T TSPC FF with retention mode was implemented as a standard cell in 65nm LP CMOS. The FF energy is 0.5fJ/cycle at 0.4V, from post-layout simulations and for a typical 25% activity factor, which is 62% reduction compared to the conventional 24T master-slave FF. Experimental validation of a prototyped Cortex-M0 testchip including the integration of the proposed FF into synthesis and place/route flow validates its robust operation at ULV.
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Citations
Moreau, L., Dekimpe, R., & Bol, D. (2019). A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. 2019 IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo (Japan). https://hdl.handle.net/2078.5/226694