Design techniques for sub-microwatt analog sensor interfaces in advanced CMOS technologies
(2013)
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- Authors
- Supervisors
- Flandre, Denis
- Abstract
- Measurement and control of industrial and natural processes are expected to grow in the near future if this technical problem can be solved : can we make a sensor system both energy autonomous and reliable? Applications are countless, and go from smart home monitoring to weather estimation or crops irrigation, to any place where a battery is too large to be used or the power grid cannot be extended to. An energy autonomous system harvests the power it needs to run from its environment exclusively. A single device using this has a low reliability as it may go offline from lack of power source. One way to cope with this problem is to have many such devices ordered in a wireless network where each node communicates when it is able to. Such systems are called wireless sensor networks (WSNs). A common statement in autonomous node design is "The energy harvested is too small, the node power consumption is too large". A wireless sensor node, part of a WSN, is composed of several subsystems (power management, sensor acquisition, data processing, memory, RF transmissions), this thesis focuses on the sensor acquisition chain, up to the digital conversion. We shall aim at developing techniques, methodologies and circuit topologies so as to lower its power consumption. Two main questions shall be asked at the beginning of this dissertation : - How can we take advantage of the most recent CMOS technologies to reduce the power consumption of the analog part of a WSN node acquisition chain? - What kind of circuit topologies and design methods can we use to improve the whole chain, especially in the analog to digital conversion? To start an answer to the first question, an improvement of the analog gm/ID design methodology is proposed to efficiently size transistors in linear analog cells using advanced CMOS technologies. The limitations of the original gm/ID methodology applied to sub-micrometer technologies are underlined by analyzing a 65 nm CMOS technology, especially variations of the transistors characteristics with drain-source voltage and length. On this basis, a complete sizing technique is presented, allowing power optimization of any linear analog cell, using the advantages of advanced technologies, while taking care of their restrictions with analog characteristics. This methodology is applied to several design cases, and compared with simulations successfully. Process, supply voltage, temperature (PVT) corners and technology portability are included in the methodology and discussed. Next, integrated in an interfacing system, an ultra low power analog to digital converter is designed, fabricated in the same 65 nm CMOS technology and characterized. It reaches an effective number of bits of 8.88 at a 100 kHz sampling rate, using only 560 nW, achieving a Walden figure of merit of 11.9 fJ/conversion-step, well comparable to the state of the art. A novel time-domain comparator is described, analyzed and integrated in the ADC design. All circuits and sub-systems are described, and non idealities and sources of errors are discussed and modeled.
- Affiliations
Citations
Pollissard, G. (2013). Design techniques for sub-microwatt analog sensor interfaces in advanced CMOS technologies. https://hdl.handle.net/2078.5/27056