State machine flattening, a mapping study and tools assessment
(2015) 8th IEEE International Conference on Software Testing, Verification and Validation — Location: Graz, Austria (13.April.2015)
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- Abstract
- State machine formalisms equipped with hierarchy and parallelism allow to compactly model complex system behaviours. Such models can then be transformed into executable code or inputs for model-based testing and verification techniques. Generated artifacts are mostly flat descriptions of system behaviour. Flattening is thus an essential step of these transformations. To assess the importance of flattening, we have defined and applied a systematic mapping process and 30 publications were finally selected. However, it appeared that flattening is rarely the sole focus of the publications and that care devoted to the description and validation of flattening techniques varies greatly. Preliminary assessment of associated tool support indicated limited tool availability and scalability on challenging models. We see this initial investigation as a first step towards generic flattening techniques and scal-able tool support, cornerstones of reliable model-based behavioural development.
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Devroey, X., Perrouin, G., Cordy, M., Schobbens, P.-Y., Heymans, P., & Legay, A. (2015). State machine flattening, a mapping study and tools assessment. 2015 IEEE Eighth International Conference on Software Testing, Verification and Validation Workshops (ICSTW). Published. 8th IEEE International Conference on Software Testing, Verification and Validation, Graz, Austria. https://doi.org/10.1109/ICSTW.2015.7107408