Source/Drain Engineered Ultra Low Power Analog/RF UTBB MOSFETs
(2011) The 12th International Conference on Ultimate Integration on Silicon – ULIS 2011 — Location: Tyndall Institute, Cork, Ireland (14.March.2011)
Files
No attached file found for this publication.
Details
- Authors
- Abstract
- We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (gm/Ids) and cut-off frequency (fT) product i.e. gmfT/Ids as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve gmfT/Ids, intrinsic voltage gain (AVO), cut-off frequency (fT) and linearity (VIP3) with downscaling.
- Affiliations
Citations
Kranti, A., Raskin, J.-P., & Armstrong, G. A. (2011). Source/Drain Engineered Ultra Low Power Analog/RF UTBB MOSFETs. Proceedings of the 12th International Conference on Ultimate Integration on Silicon – ULIS 2011, p. 114-117. https://doi.org/10.1109/ULIS.2011.5757997