VLIW processor architecture adapted to FPAs
(1998) Advanced Focal Plane Arrays and Electronic Cameras II — Location: Zurich, Switzerland (18.May.1998)
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- Authors
Legat, Jean-Didier 
- Abstract
- A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in parallel without any loss of performance. In addition, no more instruction cache is required, thus decreasing the hardware complexity.
- Affiliations
Citations
Petit, L., & Legat, J.-D. (1998). VLIW processor architecture adapted to FPAs. SPIE - the International Society for Optical Engineering. Proceedings, Vol. 3410, p. 128-132.