Effects of Back-Gate Bias on Switched-Capacitor DC-DC Converters in UTBB FD-SOI

Turnquist, Matthew J.;de Streel, Guerric;Bol, David;Hiienkari, Markus;Koskinen, lauri
(2014) 2014 IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S) — Location: San Francisco (USA) (6.October.2014)

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Authors
  • Turnquist, Matthew J.Aalto University
    Author
  • de Streel, GuerricUCLouvain
    Author
  • Bol, Davidorcid-logoUCLouvain
    Author
  • Hiienkari, MarkusUniversity of Turku, Technology Research Center
    Author
  • Koskinen, lauriUniversity of Turku, Technology Research Center
    Author
Abstract
This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FDSOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 μW load).
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Turnquist, M. J., de Streel, G., Bol, D., Hiienkari, M., & Koskinen, l. (2014). Effects of Back-Gate Bias on Switched-Capacitor DC-DC Converters in UTBB FD-SOI. 2014 IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco (USA). https://doi.org/10.1109/S3S.2014.7028200