Sizing and Layout Integrated Optimizer for 28nm Analog Circuits Using Digital PnR Tools
(2016) IEEE International NEWCAS Conference — Location: Vancouver (26.June.2016)
Files
Stas-NewCAS2016.pdf
Open Access - Adobe PDF
- 2.71 MB
Details
- Authors
- Affiliations
Citations
Stas, F., Guerric de Streel, & Bol, D. (2016). Sizing and Layout Integrated Optimizer for 28nm Analog Circuits Using Digital PnR Tools. Proc IEEE NewCAS. Published. IEEE International NEWCAS Conference, Vancouver. https://hdl.handle.net/2078.5/59039 (Original work published 2016)