Improved higher-order side-channel attacks with FPGA experiments

Peeters, Emmanuel;Quisquater, Jean-Jacques;Standaert, François-Xavier;Donckers, N
(2005) 7th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005) — Location: Edinburgh(Scotland) (29.August.2005)

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We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differential Power Analysis (DPA), we describe an improvement of the previously introduced higher-order techniques allowing us to defeat masked implementations in a low (i.e. practically tractable) number of measurements. The proposed technique is based on the efficient use of the statistical distributions of the power consumption in an actual design. It is confirmed both by theoretical predictions and practical experiments against FPGA devices.
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Peeters, E., Quisquater, J.-J., Standaert, F.-X., & Donckers, N. (2005). Improved higher-order side-channel attacks with FPGA experiments. Lecture Notes in Computer Science, 3659, 309-323. https://doi.org/10.1007/11545262_23 (Original work published 2005)