Optimization of the area/robustness/speed trade-off in a 28nm FDSOI latch based on ULP diodes
(2014) 2014 IEEE FTFC Conference — Location: Monaco (4.May.2014)
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Optimizationofthearea-robustness-speedtrade-offina28nmFDSOIlatchbasedonULPdiodes.pdf
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- Abstract
- Ultra-low-power (ULP) diodes are special 2-T structures featuring a unique negative-differential resistance characteristic that can be used to build a 4-T ULP latch for flip-flop or SRAM applications. In this paper, we explore the area/mismatch tradeoff in such a ULP latch for ultra-low-voltage (ULV) SoCs in 28 nm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6s robustness of the latch against mismatch while maintaining a leakage power below 10 pW. Under these constraints, the use of a genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both flip-flop and SRAM applications.
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Haine, T., Stas, F., & Bol, D. (2014). Optimization of the area/robustness/speed trade-off in a 28nm FDSOI latch based on ULP diodes. 2014 IEEE FTFC Conference, Monaco. https://doi.org/10.1109/FTFC.2014.6828614