A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS Image Sensor for Ultra-Low-Power SoCs achieving 40-dB Dynamic Range
(2014) 2014 IEEE Symposium on VLSI Circuits — Location: Honolulu (USA) (11.June.2014)
Files
No attached file found for this publication.
Details
- Authors
- Abstract
- A linear regulator for point of load power delivery with 280nA quiescent current and 0:008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0:5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0:5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.
- Affiliations
Citations
Bol, D., de Streel, G., Botman, F., Kuti Lusala Tsumbu-Mbi, V. A., & Couniot, N. (2014). A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS Image Sensor for Ultra-Low-Power SoCs achieving 40-dB Dynamic Range. Digest of Technical Papers, p. 180-182. https://doi.org/10.1109/VLSIC.2014.6858426