During last decades, CMOS technology scaling down has enabled high frequency operation up to mm-W and low-cost integration of digital, analog and RF systems on the same wafer for SoC or SiP applications. This fantastic success is mainly achieved thanks to the advanced node technologies with high fT and fmax fabricated on engineered HR-SOI substrates which provide good isolation between different functionalities. Standard HR-SOI substrate suffers from resistivity degradation due to the formation of parasitic surface conduction layer beneath the buried oxide layer (BOX) due to fixed oxide charges within the oxide. In addition, this phenomenon makes the substrate highly non-linear. As a solution, engineered SOI substrate as enhanced signal integrity (RFeSITM) consisting of a trap-rich layer in-between the HR handle wafer and the BOX is introduced and studied in this thesis. It is demonstrated that compared to classical HR-SOI wafer, RFeSI shows higher linearity, reduced losses, lower crosstalk, higher passive device quality factor and better thermal conductivity (due to the thinner BOX) making it able to satisfy the critical FEM requirements. By using RFeSI substrate compared to HR-SOI, more efficient SPDT switch with more than 16 dB lower 2nd harmonic and 20 dB lower coupled digital noise is achievable. Ultra-thin body and buried oxide (UTBB) technology used for fully depleted (FD) SOI MOSFETs is widely recognized as a promising candidate to continue downscaling trends beyond 28nm-node toward low power CMOS and RF-digital integration for such applications as, e.g. 5G and IoT. This thesis also provides a detailed study of this technology for RF applications in terms of fT and fmax corresponding to transistors’ front- and back-gate (BG). The small-signal equivalent circuit of the transistors is constructed from extraction of parasitic elements from which their effect on device RF performance is analyzed.