New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity
(2005) IEEE Electron Device Letters — Vol. 26, n° 11, p. 805-807 (2005)
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- Abstract
- We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.
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Lederer, D., & Raskin, J.-P. (2005). New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity. IEEE Electron Device Letters, 26(11), 805-807. https://doi.org/10.1109/LED.2005.857730 (Original work published 2005)