FPGA implementations of the DES and Triple-DES masked against power analysis attacks
(2006) 2006 International Conference on Field Programmable Logic and Applications — Location: Madrid, Spain (28.August.2006)
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- This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular, we use the large embedded memories available in the Xilinx Virtex-II pro reg FPGAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec.
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Standaert, F.-X., Quisquater, J.-J., & Rouvroy, G. (2006). FPGA implementations of the DES and Triple-DES masked against power analysis attacks. In Koch, A.; Leong, P.; Boemo, E.; (ed.), Proceedings 2006 International Conference on Field Programmable Logicand Applications (FPL) (p. p. 791-794). IEEE. https://hdl.handle.net/2078.5/221662