A 2-mW power consumption low noise amplifier in PD SOI CMOS technology for 2.4 GHz applications
(2006) 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems — Location: Long Beach, CA, USA (10.January.2007)
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- Abstract
- This paper reviews and analyzes a fully integrated low-noise amplifier (LNA) for low-power and narrow-band applications using a cascode inductive source degeneration topology, with a body contacted transistor in 130 nm partially depleted CMOS SOI technology. Thanks to the SOI technology, the LNA shows only 2 mW power consumption when power gain of 10 dB and a noise figure of 3.1 dB at 2.4 GHz are measured for 1.2 V supply voltage.
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Citations
El Kaamouchi, M., Si Moussa, M., Raskin, J.-P., & Vanhoenacker-Janvier, D. (2006). A 2-mW power consumption low noise amplifier in PD SOI CMOS technology for 2.4 GHz applications. 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RFSystems (IEEE Cat No. 07EX1459C), 4 pp. https://hdl.handle.net/2078.5/230984