Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface
(2009) IEEE Electron Device Letters — Vol. 30, n° 11, p. 1197-1199 (2009)
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- Abstract
- This letter presents a detailed investigation of the impact of dopant segregation (DS) on radio-frequency (RF) performance of p-type 110-nm undoped ultrathin-body Schottky-barrier (SB) silicon-on-insulator MOSFETs. It is shown that optimizing this dopant-segregated layer via careful control of the dopant concentration (N-SEG) and lateral extension (L-SEG) reduces the apparent potential barrier height at the Schottky junctions. This results in highly reduced source/drain (S/D) contact resistances, along with a peak f(T) value obtained at very low dc power consumption (45 mu W/mu m at V-DS = -2 V), which is very promising to address low-power low-voltage analog applications. Finally, the source resistance extracted from this RF study (similar to 120 Omega . mu m) clearly demonstrates the ability of the DS SB S/D architecture to pursue the silicon roadmap beyond the 22-nm node.
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Valentin, R., Dubois, E., Larrieu, G., Raskin, J.-P., Dambrine, G., Breil, N., & Danneville, F. (2009). Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface. IEEE Electron Device Letters, 30(11), 1197-1199. https://doi.org/10.1109/LED.2009.2031254 (Original work published 2009)