Hole electrical transport in a p-doped nanochannel defined between two L-shape etched trenches made on a silicon-on-insulator substrate is investigated using a TCAD-Medici simulator. We study the impact of the etched trenches' geometry and dielectric filling materials on the current–voltage characteristics of the device. Carrier accumulation on frontiers defined by the trenches causes a modulation of the hole density inside the conduction channel as the bias voltage varies and this gives rise to a diode-like characteristic. For a 1.2 µm-long channel, plots of the electric field distribution show that a nonlinear transport regime is reached at a moderate reverse and forward bias of ± 2 V. Plots of the carrier velocity along the conduction channel show that holes remain hot for a few hundreds of nm outside the nanometre-wide channel, at a bias of ± 10 V. Filling the etched trenches with a high-κ dielectric material gives rise to a lower threshold voltage, Vth. A similar decrease of Vth is also achieved by reducing the longitudinal and/or the transverse trench width. Our simulation results provide useful design guidelines for future integrated self-switching-diode-based circuits.
Farhi, G., Morris, D., Charlebois, S. A., & Raskin, J.-P. (2011). The impact of etched trenches geometry and dielectric material on the electrical behaviour of SOI self-switching diodes. Nanotechnology, 22(43), 435203. https://doi.org/10.1088/0957-4484/22/43/435203 (Original work published 2011)