SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping

de Streel, Guerric;Stas, François;Gurné, Thibaut;Durant, François;Bol, David;et.al.
(2017) IEEE Journal of Solid State Circuits — Vol. 52, n° 4, p. 1163-1177 (2017)

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Authors
  • de Streel, GuerricUCLouvain
    Author
  • Stas, FrançoisUCLouvain
    Author
  • Gurné, ThibautNokia Bell Labs, Antwerpen/Belgium
    Author
  • Durant, FrançoisVerotech BVBA, Leuven/Belgium
    Author
  • Frenkel, CharlotteUCLouvain
    Author
  • Bol, Davidorcid-logoUCLouvain
    Author
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Abstract
Achieving wireless communications at 5–30 Mb/s in energy-harvesting Internet-of-Things (IoT) applications requires energy efficiencies better than 100 pJ/b. Impulse-radio ultra-wideband (UWB) communications offer an efficient way to achieve high data rate at ultra-low power for short-range links. We propose a digital UWB transmitter (TX) system-on-chip (SoC) designed for ultra-low voltage in 28-nm FDSOI CMOS. It features a PLL-free architecture, which exploits the duty-cycling nature of impulse radio through aggressive duty cycling within the pulse modulation time slot for high energy efficiency and minimum jitter accumulation. Wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. To ensure spectral compliance with output power regulations without the use of bulky and expensive off-chip filters, a programmable pulse-shaping functionality is integrated in the digital power amplifier based on a 7–9-GS/s, 5-b current DAC. Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the TX alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.
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de Streel, G., Stas, F., Gurné, T., Durant, F., Frenkel, C., Cathelin, A., & Bol, D. (2017). SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. IEEE Journal of Solid State Circuits, 52(4), 1163-1177. https://doi.org/10.1109/JSSC.2016.2645607 (Original work published 2017)