Leakage-Resilient Circuit Garbling
(2024) ACM CCS 2024 — Location: Salt Lake City, USA
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- Abstract
- Due to the ubiquitous requirements and performance leap in the past decade, it has become feasible to execute garbling and se- cure computations in settings sensitive to side-channel attacks, including smartphones, IoTs and dedicated hardwares, and the possibilities have been demonstrated by recent works. To maintain security in the presence of a moderate amount of leaked information about internal secrets, we investigate leakage-resilient garbling. We augment the classical privacy, obliviousness and authenticity notions with leakages of the garbling func- tion, and define their leakage-resilience analogues. We examine popular garbling schemes and unveil additional side-channel weaknesses due to wire label reuse and XOR leakages. We then incorporate the idea of label refreshing into the GLNP garbling scheme of Gueron et al. and propose a variant GLNPLR that provably satisfies our leakage-resilience defini- tions. Performance comparison indicates that GLNPLR is 60X (using AES-NI) or 5X (without AES-NI) faster than the HalfGates garbling with second order side-channel masking, for garbling AES circuit when the bandwidth is 2Gbps.
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Citations
Ruiyang Li, Yiteng Sun, Guo, C., Standaert, F.-X., Wang, W., & Xiao Wang. (2024). Leakage-Resilient Circuit Garbling. Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, p. 780-794. https://doi.org/10.1145/3658644.3690204