Enhanced high resistivity SOI wafers for RF applications
(2004) 2004 IEEE International SOI Conference — Location: Charleston, South Carolina, USA (4.October.2004)
Files
No attached file found for this publication.
Details
- Authors
- Abstract
- In this work, we investigate the impact of distinctly processed trap-rich layers of polysilicon inserted between BOX and HR Si substrate on the effective resistivity, substrate losses and crosstalk level in HR SOI wafers. The wafers were fabricated starting from p-type high resistivity bulk wafers with resistivity higher than 3 kΩ.cm. The wafers were first covered with a LPCVD layer of undoped polysilicon at 2 distinct temperatures (Tpoly=585 °C, 625 °C) and with varying thickness. This layer was afterwards passivated with a charge rich 3 μm thick PECVD oxide of the reference wafer. The oxide layer was densified by RTA at 800 °C during 20 s.
- Affiliations
Citations
Lederer, D., Lobet, R., & Raskin, J.-P. (2004). Enhanced high resistivity SOI wafers for RF applications. Proceedings of the 2004 IEEE International SOI Conference, pp. 46-47. https://doi.org/10.1109/SOI.2004.1391549