Large array-based circuits in ULV SoCs : design and statistical assessment of SRAMs and CMOS imagers
(2018)
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- Authors
- Supervisors
- Bol, David
- Abstract
- The connection of everyday-life objects to the internet is steadily growing thanks to smarter and smarter sensors. In such Internet-of-Things applications, the lifetime of the system is of critical importance. The smart sensor needs to operate as long as possible on small batteries or even on power harvested from the environment. Fitting the sensing, data processing and RF communication to the cloud in this tight power budget is very challenging and requires ultra-low power (ULP) circuits. Minimizing the power/energy consumption has thus become an active research direction over the past few years. In this thesis, we focus on two types of circuits that can be found in ULP smart sensors: static random access memories (SRAMs) and CMOS imagers. These two circuits are both based on a large array of replicated elements: the bitcell for the SRAM and the pixel for the imager. Due to the high number of replicated instances (>100 000), the robustness of these elements is of utmost importance as a single faulty element can impede the smart sensor functionality. As we aim for a very low failure rate, a huge number of SPICE Monte Carlo simulations have to be performed to assess the failure rate of such circuits. Performing these numerous simulations is so time consuming that it becomes impractical in reality. In the first part of this thesis, a new methodology called “Gradient Importance Sampling” is proposed to quickly extract low failure rate from a limited number of simulation runs. The second part of this thesis concerns the design of ULP SRAMs. SRAM are a key element of every processor as they are used to store instructions and data. In today's design, they occupy an ever growing portion of the circuit area as well as an important part of the power budget. Two ULP SRAM prototypes have been designed with a custom low-power bitcell. They both feature very low leakage power and access energy compared to the state of the art. The final part of this dissertation is focused on the design of a ULP CMOS imager for a surveillance application. Based on previous work, two generations of ULP imagers have been designed. Improvements in the architecture have been introduced to further decrease power consumption. In addition motion detection and pixel aggregation have been embedded in the design of the second generation to decrease the power of the whole surveillance system.
- Affiliations
Citations
Haine, T. (2018). Large array-based circuits in ULV SoCs : design and statistical assessment of SRAMs and CMOS imagers. https://hdl.handle.net/2078.5/57421