Transient floating-body effects for memory applications in fully-depleted SOI MOSFETs
(2007)
Files
Bawedin.pdf
Restricted Access - Adobe PDF
- 8.37 MB
Details
- Authors
- Supervisors
- Abstract
- Memory devices based on floating-body effects (FBE) in Silicon-on-Insulator (SOI) technology are among the most promising candidates for sub-100nm and low power Dynamic Random Access Memory (DRAM). This new type of DRAMs, called Zero Capacitor RAM (Z-RAM), uses only one transistor in partially-depleted (PD) SOI technology and takes advantage of FBE which have been considered as parasitic phenomena until now. The Z-RAM programming principles are based on the threshold voltage Vth variations induced by the excess or lack of majority carriers in the floating body. In this dissertation, a new floating-body effect, the Transient Floating Body Potential Effect (TFBPE), based on the body majority carriers non-equilibrium and on the dual dynamic gate coupling in standard fully-depleted (FD) SOI MOSFETs is presented for the first time. The TFBPE occurs in a specific gate bias range and can induce strong hysteresis of the gate and drain current characteristics although the FD SOI transistors are usually known to be immune against the FBE and their aftermaths. Adapted from the same physics principles as in the drain current hysteresis, that we called the Meta-Stable Dip (MSD) effect, a new concept of one-transistor capacitor-less memory was also proposed, the Meta-Stable DRAM (MSDRAM). All the experimental results and physics interpretations were supported by 2D numerical simulations and a 1D semi-analytical model of the body potential for non-equilibrium states was also proposed. First, the 1D semi-analytical model in case of TFBPE is presented. For the first time, this original body-potential model takes into account the majority carriers density variations, i.e., the quasi-Fermi level non-equilibrium versus a transient gate voltage scan in a FD MOS device. Our model is valid for a wide range of technological parameters and shows several advantages such as implementation simplicity, low computation time and injection currents splitting which was very useful for the TFBPE physics interpretations. Next, systematic experimental characteristics of the transient gate current and drain current hysteresis (MSD effect) were provided. The physics interpretations were supported by our 1D modeling and 2D numerical simulation results. Finally, our new concept of one-transistor capacitor-less DRAM, the MSDRAM dedicated for Double-Gate (DG) operations and using the same principles as the MSD effect, was presented. The MSDRAM fundaments lie in dynamic dual gate coupling and are not based on the Vth variations as in the Z-RAM. Experimental data of standard FD SOI MOSFETs were used to validate the MSDRAM concepts, and 2D numerical simulations were provided for further DG-MSDRAM applications. As for Z-RAM, the main advantages are the cell size reduction and the non-destructive read, but in addition, the MSDRAM provides a stable 1-state and long retention time even with very short channel lengths (down to 50nm).
- Affiliations
Citations
Bawedin, M. (2007). Transient floating-body effects for memory applications in fully-depleted SOI MOSFETs. https://hdl.handle.net/2078.5/98470