LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide
(2010) IEEE Transactions on Electron Devices — Vol. 57, n° 6, p. 1319-1326 (2010)
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- Abstract
- We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltageΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported.
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Yan, R., Duane, R., Razavi, P., Afzalian, A., Ferain, I., Lee, C.-W., Dehdashti Akhavan, N., Nguyeb, B.-Y., Bourdelle, K. K., & Colinge, J.-P. (2010). LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide. IEEE Transactions on Electron Devices, 57(6), 1319-1326. https://doi.org/10.1109/TED.2010.2046097 (Original work published 2010)