Impact of extrinsic capacitances on FinFETs RF performance

Tinoco, J.C.;Alvarado, J.;Martinez-Lopez, A.G.;Raskin, Jean-Pierre
(2012) IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - SiRF 2012 — Location: Santa Clara, CA, USA (16.January.2012)

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  • Tinoco, J.C.Depto. de Ing. en Telecommun., UNAM, Mexico City, Mexico
    Author
  • Alvarado, J.Depto. de Ing. en Telecommun., UNAM, Mexico City, Mexico
    Author
  • Martinez-Lopez, A.G.Depto. de Ing. en Telecommun., UNAM, Mexico City, Mexico
    Author
  • Raskin, Jean-PierreUCLouvain
    Author
Abstract
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations we analyze the impact of the extrinsic gate capacitance on the RF behavior of FinFETs. It observes that the extrinsic capacitances are larger than the intrinsic counterparts for sub-100 nm devices. Furthermore, the reduction of the fin spacing as well as the increase of the fin geometrical aspect ratio (height/width) can improve significantly the FinFETs RF behavior.
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Tinoco, J. C., Alvarado, J., Martinez-Lopez, A. G., & Raskin, J.-P. (2012). Impact of extrinsic capacitances on FinFETs RF performance. Proceedings of the IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - SiRF 2012, pp. 73-76. https://doi.org/10.1109/SiRF.2012.6160141