RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate
(2014) IEEE Transactions on Electron Devices — Vol. 61, n° 3, p. 722-728 (2014)
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- Abstract
- RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications. © 1963-2012 IEEE.
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Ali, K. B., Neve, C. R., Gharsallah, A., & Raskin, J.-P. (2014). RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate. IEEE Transactions on Electron Devices, 61(3), 722-728. https://doi.org/10.1109/TED.2014.2302685 (Original work published 2014)